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| ht1650 64 32 lcd controller for i/o mcu patented pat no. : 099352 rev. 1.80 1 november 9, 2010 features operating voltage: 2.7v~5.2v built-in 32khz rc oscillator external 32.768khz crystal oscillator or 32khz fre - quency source input standby current: <1 a at 3v, <2 aat5v internal resistor type: 1/6 bias or 1/5 bias, 1/32 duty, and 1/16 duty three selectable lcd frame frequencies: 64hz, 89hz or 170hz max. of 64 32 patterns, 64 segments and 32 com - mons 80 segments and 16 commons selectable by com- mand method built-in bit-map display ram: 2048 bits (=64 32 bits) built-in internal resistor type bias generator six-wire interface (four data wires) eight kinds of time base or wdt selection time base or wdt overflow output r/w address auto increment built-in buzzer driver (2khz/4khz) power down command reduces power consumption software configuration feature data mode and command mode instructions three data accessing modes provides vlcd pin to adjust lcd operating voltage and max. vlcd voltage up to 7v provides three kinds of bias current programming control of tn-type and stn-type lcds 128-pin qfp package general description ht1650 is a peripheral device specially designed for i/o type mcus which are used to expand the display capa - bility. the max. display segment of the device are 2048 patterns (64 segments and 32 commons). it also sup - ports four data bits interface, buzzer sound, watchdog timer or time base timer functions. the ht1650 is a memory mapping and multi-function lcd controller. it can control tn-type (twisted nematic) or stn-type (super twisted nematic) lcds. the software configu - ration feature of the ht1650 make it suitable for multiple lcd applications including lcd modules and display subsystems. only six lines (cs ,wr , db0~db3) are re - quired for the interface between the host controller and the ht1650. applications leisure products games personal digital assistant cellular phone global positioning system consumer electronics technical document tools information faqs application note
block diagram pin assignment ht1650 rev. 1.80 2 november 9, 2010 patented ! " # " ! $ ! % & " ' $ " ' ( % ) * + + # , - " " - - ! " ! $ % . / " / + 0 + / 0 / # ' 1 0 ' 1 $ 2 % / 3 ! $ 2 ! % & 0 " ' $ 2 " ' ( % / # , / 3 4 5 & 6 (& 6 7 " ' & 6 " ' & & " ' & $ " ' 8 " ' 9 " ' 7 " ' ( " ' : " ' ; " ' % " ' 6 " ' & " ' $ ! & : ! & ; ! & % ! & 6 ! & & ! & $ ! 8 ! 9 ! 7 ! ( ! : ! ; ! % ; & ; 6 ; % ; ; ; : ; ( ; 7 ; 9 ; 8 : $ ; $ : & : 6 : % & 6 % ; : ( 7 9 8 & $ & & & 6 & % & ; & : & ( & 7 & 9 & 8 6 $ 6 & 6 6 6 % 6 ; 6 : 6 ( 6 7 6 9 6 8 % $ % & % 6 % % % ; % : % ( % 7 % 9 & 6 9 ! & 9 ! & 7 ! & ( . . . . . . " $ & 6 % - " " ! " # ! " ! - - # , + + & 6 % ; $ $ $ - . . . . . ! $ ! & ! 6 % 8 : ; : : : ( : 7 : 9 : 8 ( $ ( & ( 6 ( % ( ; " ' : $ " ' ; 8 " ' ; 9 " ' ; 7 " ' ; ( " ' ; : " ' ; ; " ' ; % " ' ; 6 " ' ; & " ' ; $ " ' % 8 " ' % 9 " ' % 7 " ' % ( " ' % : " ' % ; " ' % % " ' % 6 " ' % & " ' % $ " ' 6 8 " ' 6 9 " ' 6 7 " ' 6 ( " ' 6 : " ' 6 ; " ' 6 % " ' 6 6 " ' 6 & " ' 6 $ " ' & 8 " ' & 9 " ' & 7 " ' & ( " ' & : " ' & ; " ' & % " ' : & " ' : 6 " ' : % " ' : ; " ' : : " ' : ( " ' : 7 " ' : 9 " ' : 8 " ' ( $ " ' ( & " ' ( 6 " ' ( % ! % & ! % $ ! 6 8 ! 6 9 ! 6 7 ! 6 ( ! 6 : ! 6 ; ! 6 % ! 6 6 ! 6 & ! 6 $ ! & 8 & 6 : & 6 6& 6 % & 6 ; & 6 & & 6 $ & & 8 & & 9 & & 7 & & ( & & : & & ; & & % & & 6 & & & & & $ & $ 8 & $ 9 & $ 7 & $ ( & $ : & $ ; & $ % & $ 6 & $ & & $ $ 8 8 8 9 8 7 8 ( 8 : 8 ; 8 % 8 6 8 & 8 $ 9 8 9 9 9 7 9 ( 9 : 9 ; 9 % 9 6 9 & 9 $ 7 8 7 9 7 7 7 ( 7 : 7 ; 7 % 7 6 7 & 7 $ ( 8 ( 9 ( 7 ( ( ( : pad assignment chip size: 3555 3970 (m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. pad coordinates unit: m pad no. x y pad no. x y pad no. x y 1 1329.500 1880.000 40 383.700 1784.900 79 1672.500 382.400 2 1672.500 1738.050 41 293.700 1784.900 80 1672.500 495.400 3 1672.500 1359.300 42 190.500 1784.900 81 1672.500 608.400 4 1672.500 1249.300 43 95.000 1784.900 82 1672.500 721.400 5 1672.500 1129.300 44 5.300 1784.900 83 1672.500 834.400 6 1672.500 1007.500 45 111.400 1853.850 84 1672.500 947.400 7 1672.500 887.500 46 183.950 1753.850 85 1672.500 1060.400 8 1672.500 765.700 47 308.850 1794.400 86 1672.500 1173.400 9 1672.500 645.700 48 414.450 1794.400 87 1672.500 1286.400 10 1672.500 523.900 49 509.450 1794.400 88 1672.500 1736.100 11 1672.500 403.900 50 630.250 1770.250 89 1425.500 1880.000 12 1672.500 282.100 51 743.850 1770.250 90 1330.500 1880.000 ht1650 rev. 1.80 3 november 9, 2010 patented & < $ 0 $ = 6 % ; : ( 7 9 8 & $ & & & 6 & % & ; & : & ( & 7 & 9 & 8 6 $ 6 & 6 6 6 % 6 ; 6 : 6 ( 6 7 6 9 6 8 % $ % & % 6 % % % ; % : % ( % 7 % 9 % 8 ; $ ; & ; 6 ; % ; ; ; : ; ( ; 7 ; 9 ; 8 : $ : & : 6 : % : ; : : : ( : 7 9 9 9 7 9 ( 9 : 9 ; 9 % 9 6 9 & 9 $ 7 8 7 9 7 7 7 ( 7 : 7 ; 7 % 7 6 7 & 7 $ ( 8 ( 9 ( 7 ( ( ( : ( ; ( % ( 6 ( & ( $ : 8 : 9 9 8 8 $ 8 & 8 6 8 % 8 ; 8 : 8 ( 8 7 8 9 8 8 & $ $ & $ & & $ 6 & $ % & $ ; & $ : & $ ( & $ 7 & $ 9 & $ 8 & & $ & & & & & 6 & & % & & ; & & : & & ( & & 7 " ' ; 7 " ' ; 9 " ' ; 8 " ' : $ " ' : & " ' : 6 " ' : % " ' : ; " ' : : " ' : ( " ' : 7 " ' : 9 " ' : 8 " ' ( $ " ' ( & " ' ( 6 " ' ( % ! % & ! % $ ! 6 8 ! 6 9 ! 6 7 ! 6 ( ! 6 : ! 6 ; ! 6 % ! 6 6 ! 6 & ! 6 $ ! & 8 ! & ( ! & 7 ! & 9 ! & ! $ - $ $ $ ; % 6 & + + # , - - ! " ! ! " # - " " % 6 & " $ " ' & ( " ' & : " ' & ; " ' & % " ' & 6 " ' & & " ' & $ " ' 8 " ' 9 " ' 7 " ' ( " ' : " ' ; " ' % " ' 6 " ' & " ' $ ! & : ! & ; ! & % ! & 6 ! & & ! & $ ! 8 ! 9 ! 7 ! ( ! : ! ; ! % ! 6 " ' & 7 " ' & 9 " ' & 8 " ' 6 $ " ' 6 & " ' 6 6 " ' 6 % " ' 6 ; " ' 6 : " ' 6 ( " ' 6 7 " ' 6 9 " ' 6 8 " ' % $ " ' % & " ' % 6 " ' % % " ' % ; " ' % : " ' % ( " ' % 7 " ' % 9 " ' % 8 " ' ; $ " ' ; & " ' ; 6 " ' ; % " ' ; ; " ' ; : " ' ; ( pad no. x y pad no. x y pad no. x y 13 1672.500 162.100 52 857.450 1770.250 91 1235.500 1880.000 14 1672.500 40.300 53 971.050 1770.250 92 1140.500 1880.000 15 1672.500 79.700 54 1084.650 1770.250 93 1045.500 1880.000 16 1672.500 201.500 55 1206.800 1848.100 94 950.500 1880.000 17 1672.500 321.500 56 1330.200 1880.000 95 855.500 1880.000 18 1672.500 416.500 57 1427.200 1880.000 96 760.500 1880.000 19 1672.500 511.500 58 1672.500 1880.000 97 665.500 1880.000 20 1672.500 606.500 59 1672.500 1643.600 98 570.500 1880.000 21 1672.500 701.500 60 1672.500 1548.600 99 475.500 1880.000 22 1672.500 796.500 61 1672.500 1453.600 100 380.500 1880.000 23 1672.500 891.500 62 1672.500 1358.600 101 285.500 1880.000 24 1672.500 986.500 63 1672.500 1263.600 102 190.500 1880.000 25 1672.500 1081.500 64 1672.500 1168.600 103 95.500 1880.000 26 1672.500 1176.500 65 1672.500 1073.600 104 0.500 1880.000 27 1672.500 1271.500 66 1672.500 978.600 105 94.500 1880.000 28 1672.500 1366.500 67 1672.500 883.600 106 189.500 1880.000 29 1672.500 1461.500 68 1672.500 788.600 107 284.500 1880.000 30 1672.500 1556.500 69 1672.500 693.600 108 379.500 1880.000 31 1672.500 1651.500 70 1672.500 598.600 109 474.500 1880.000 32 1208.550 1880.000 71 1672.500 503.600 110 569.500 1880.000 33 1113.550 1880.000 72 1672.500 408.600 111 664.500 1880.000 34 1018.550 1880.000 73 1672.500 295.600 112 759.500 1880.000 35 895.500 1784.900 74 1672.500 182.600 113 854.500 1880.000 36 789.900 1784.900 75 1672.500 69.600 114 949.500 1880.000 37 694.900 1784.900 76 1672.500 43.400 115 1044.500 1880.000 38 589.300 1784.900 77 1672.500 156.400 116 1139.500 1880.000 39 494.300 1784.900 78 1672.500 269.400 117 1234.500 1880.000 pad description pad no. pad name i/o description 1~17 71~117 seg47~seg63 seg0~seg46 o lcd segment outputs 18~33 55~70 com31~com16 com0~com15 o lcd common outputs, under 80 16 command mode, com16~com31 will be shared with seg64~seg79. com31/seg64, com30/seg65, com29/seg66....., com18/seg77, com17/seg78, com16/seg79 34 cs i chip selection input with pull-high resistor. when the cs is logic high, the data and command read from or write to the ht1650 are disabled. the serial inter - face circuit is also reset. but if the cs is at a logic low level and is input to the cs pad, the data and command transmission between the host controller and the ht1650 are all enabled. 35 rd i read clock input with pull-high resistor. data in the ram of the ht1650 are clocked out on the falling edge of the rd signal. the clocked out data will ap - pear on the data line. the host controller can use the next rising edge to latch the clocked out data. 36 wr i write clock input with pull-high resistor. data on the data line are latched into the ht1650 on the rising edge of the wr signal. 37~40 db0~db3 i/o parallel data input/output with pull-high resistor 41 vss negative power supply for logic circuit, ground 42 43 osci osco i o the osci and osco pads are connected to a 32.768khz crystal in order to generate a system clock. if the system clock comes from an external clock source, the external clock source should be connected to the osci pad. but if an on-chip rc oscillator is selected, the osci and osco pads can be left open. 44 vdd positive power supply for logic circuit 45 vlcd i power supply for lcd driver circuit ht1650 rev. 1.80 4 november 9, 2010 patented pad no. pad name i/o description 46 irq o time base or watchdog timer overflow flag, nmos open drain output. 47, 48 bz, bz o 2khz or 4khz frequency output pair (tristate output buffer) 49~53 t1~t4, t000 i vary bias current pin it is usually not connected absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +5.5v storage temperature ............................ 50 cto125 c input voltage.............................v ss 0.3v to v dd +0.3v operating temperature........................... 25 cto75 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 2.7 5.2 v i dd1 operating current 3v no load/lcd on on-chip rc oscillator 150 250 a 5v 250 370 a i dd2 operating current 3v no load/lcd on crystal oscillator 135 200 a 5v 200 300 a i dd11 operating current 3v no load/lcd off on-chip rc oscillator 15 30 a 5v 50 70 a i dd22 operating current 3v no load/lcd off crystal oscillator 210 a 5v 310 a i stb standby current 3v no load, power down mode 1 a 5v 2 a v il input low voltage 3v db0~db3, wr ,cs ,rd 0 0.6 v 5v 0 1.0 v v ih input high voltage 3v db0~db3, wr ,cs ,rd 2.4 3v 5v 4.0 5v i ol1 bz, bz , irq sink current 3v v ol =0.3v 1.2 2.5 ma 5v v ol =0.5v 36 ma i oh1 bz, bz source current 3v v oh =2.7v 0.9 1.8 ma 5v v oh =4.5v 2 4 ma i ol2 db0~db3 sink current 3v v ol =0.3v 1.2 2.5 ma 5v v ol =0.5v 36 ma i oh2 db0~db3 source current 3v v oh =2.7v 0.9 1.8 ma 5v v oh =4.5v 2 4 ma i ol3 lcd common sink current 3v v ol =0.3v 80 160 a 5v v ol =0.5v 180 360 a i oh3 lcd common source current 3v v oh =2.7v 40 80 a 5v v oh =4.5v 90 180 a ht1650 rev. 1.80 5 november 9, 2010 patented symbol parameter test conditions min. typ. max. unit v dd conditions i ol4 lcd segment sink current 3v v ol =0.3v 50 100 a 5v v ol =0.5v 120 240 a i oh4 lcd segment source current 3v v oh =2.7v 30 60 a 5v v oh =4.5v 70 140 a r ph pull-high resistor 3v db0~db3, wr ,cs ,rd 150 250 410 k 5v 60 125 210 k a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock 3v on-chip rc oscillator 22 32 40 khz 5v 24 32 40 khz f sys2 system clock 3v crystal oscillator 32.768 khz 5v 32.768 khz f sys3 system clock 3v external clock source 32 khz 5v 32 khz f lcd1 lcd frame frequency 3v on-chip rc oscillator 61/117 89/170 111/213 hz 5v 61/117 89/170 111/213 hz f lcd2 lcd frame frequency 3v crystal oscillator 64 hz 5v 64 hz f lcd3 lcd frame frequency 3v external clock source 64 hz 5v 64 hz t com lcd common period n: number of com n/f lcd sec f clk1 4-bit data clock (wr pin) 3v duty cycle 50% 150 khz 5v 300 khz f clk2 4-bit data clock (rd pin) 3v duty cycle 50% 75 khz 5v 150 khz t cs 4-bit interface reset pulse width (figure 3) cs 250 ns t clk wr ,rd input pulse width (figure 1) 3v write mode 3.34 s read mode 6.67 5v write mode 1.67 s read mode 3.34 t r ,t f rise/fall time serial data clock width (figure 1) 3v 120 ns 5v t su setup time for db to wr ,rd clock width (figure 2) 3v 120 ns 5v t h hold time for db to wr ,rd clock width (figure 2) 3v 120 ns 5v t su1 setup time for cs to wr ,rd clock width (figure 3) 3v 100 ns 5v t h1 hold time for cs to wr ,rd clock width (figure 3) 3v 100 ns 5v ht1650 rev. 1.80 6 november 9, 2010 patented ht1650 rev. 1.80 7 november 9, 2010 patented 8 $ > : $ > & $ > . 0 1 ? 4 ? - figure 1 : $ > - : $ > . . 0 1 - figure 2 functional description system oscillator the ht1650 system clock is used to generate the time base or watchdog timer (wdt) clock frequency, lcd driving clock, and tone frequency. the clock source may be from an on-chip rc oscillator (32khz), a crystal oscil - lator (32.768khz), or an external 32khz clock by the s/w setting. the configuration of the system oscillator is as shown. after the sys dis command is executed, the system clock will stop and the lcd bias generator will turn off. that command is available only for the on-chip rc oscillator or for the crystal oscillator. once the sys- tem clock stops, the lcd display will become blank, and the time base/wdt loses its function as well. the lcd off command is used to turn the lcd bias generator off. after the lcd bias generator switches off by issuing the lcd off command, using the sys dis command reduces power consumption, thus serving as a system power down command. but if the external clock source is chosen as the system clock, using the sys dis command can neither turn the oscillator off nor carry out the power down mode. the crystal oscillator option can be applied to connect an external frequency source of 32khz to the osci pin. in this case, the sys- tem fails to enter the power down mode, similar to the case of the external 32khz clock source operation. at the initial system power on, the ht1650 is at the sys dis state. ! " # ! " ! ! % 6 7 ( 9 @ a ' b 1 " % 6 1 @ a ! c ! % 6 1 @ a " 1 system oscillator configuration " . : $ > : $ > ) 1 1 . 0 1 & & " - - figure 3 ht1650 rev. 1.80 8 november 9, 2010 patented display memory ram structure the static display ram is organized into 512 4 bits and stores the display data. the contents of the ram are directly mapped to the contents of the lcd driver. data in the ram can be accessed by the read, write and read-modify-write commands. the following is a mapping from the ram to the lcd patterns. 00h 08h 10h 18h 20h--------- 1d8h 1e0h 1e8h 1f0h 1f8h com0 bit0 bit0 bit0 bit0 bit0 com1 bit1 bit1 bit1 bit1 bit1 com2 bit2 bit2 bit2 bit2 bit2 com3 bit3 bit3 bit3 bit3 bit3 01h 09h 11h 19h 21h--------- 1d9h 1e1h 1e9h 1f1h 1f9h com4 bit0 bit0 bit0 bit0 bit0 com5 bit1 bit1 bit1 bit1 bit1 com6 bit2 bit2 bit2 bit2 bit2 com7 bit3 bit3 bit3 bit3 bit3 02h 0ah 12h 1ah 22h--------- 1dah 1e2h 1eah 1f2h 1fah com8 bit0 bit0 bit0 bit0 bit0 com9 bit1 bit1 bit1 bit1 bit1 com10 bit2 bit2 bit2 bit2 bit2 com11 bit3 bit3 bit3 bit3 bit3 03h 0bh 13h 1bh 23h--------- 1dbh 1e3h 1ebh 1f3h 1fbh com12 bit0 bit0 bit0 bit0 bit0 bit0 com13 bit1 bit1 bit1 bit1 bit1 bit1 com14 bit2 bit2 bit2 bit2 bit2 bit2 com15 bit3 bit3 bit3 bit3 bit3 bit3 04h 0ch 14h 1ch 24h--------- 1dch 1e4h 1ech 1f4h 1fch com16 bit0 bit0 bit0 bit0 bit0 bit0 com17 bit1 bit1 bit1 bit1 bit1 bit1 com18 bit2 bit2 bit2 bit2 bit2 bit2 com19 bit3 bit3 bit3 bit3 bit3 bit3 05h 0dh 15h 1dh 25h--------- 1ddh 1e5h 1edh 1f5h 1fdh com20 bit0 bit0 bit0 bit0 bit0 bit0 com21 bit1 bit1 bit1 bit1 bit1 bit1 com22 bit2 bit2 bit2 bit2 bit2 bit2 com23 bit3 bit3 bit3 bit3 bit3 bit3 06h 0eh 16h 1eh 26h--------- 1deh 1e6h 1eeh 1f6h 1feh com24 bit0 bit0 bit0 bit0 bit0 bit0 com25 bit1 bit1 bit1 bit1 bit1 bit1 com26 bit2 bit2 bit2 bit2 bit2 bit2 com27 bit3 bit3 bit3 bit3 bit3 bit3 07h 0fh 17h 1fh 27h--------- 1dfh 1e7h 1efh 1f7h 1ffh com28 bit0 bit0 bit0 bit0 bit0 bit0 com29 bit1 bit1 bit1 bit1 bit1 bit1 com30 bit2 bit2 bit2 bit2 bit2 bit2 com31 bit3 bit3 bit3 bit3 bit3 bit3 seg0 seg1 seg2 seg3 seg60 seg61 seg62 seg63 64 32 selection mode ram mapping table ht1650 rev. 1.80 9 november 9, 2010 patented 00h 04h 08h 0ch 10h------- 12ch 130h 134h 138h 13ch com0 bit0 bit0 bit0 bit0 bit0 com1 bit1 bit1 bit1 bit1 bit1 com2 bit2 bit2 bit2 bit2 bit2 com3 bit3 bit3 bit3 bit3 bit3 01h 05h 09h 0dh 11h--------- 12dh 131h 135h 139h 13dh com4 bit0 bit0 bit0 bit0 bit0 com5 bit1 bit1 bit1 bit1 bit1 com6 bit2 bit2 bit2 bit2 bit2 com7 bit3 bit3 bit3 bit3 bit3 02h 06h 0ah 0eh 12h--------- 12eh 132h 136h 13ah 13eh com8 bit0 bit0 bit0 bit0 bit0 com9 bit1 bit1 bit1 bit1 bit1 com10 bit2 bit2 bit2 bit2 bit2 com11 bit3 bit3 bit3 bit3 bit3 03h 07h 0bh 0fh 13h--------- 12fh 133h 137h 13bh 13fh com12 bit0 bit0 bit0 bit0 bit0 bit0 com13 bit1 bit1 bit1 bit1 bit1 bit1 com14 bit2 bit2 bit2 bit2 bit2 bit2 com15 bit3 bit3 bit3 bit3 bit3 bit3 seg0 seg1 seg2 seg3 seg76 seg77 seg78 seg79 80 16 selection mode ram mapping table name command code function 80 16 mode x100 -0001-1111-xxxx change segment from 64 to 80 and common from 32 to 16 the default value after power on reset is 64 32 mode, set normal command will change 80 16 mode to 6432 mode. frame frequency the ht1650 provides three kinds of frame frequency options by command code; 64hz, 89hz and 170hz respectively. frame 64hz provides 64hz frame frequency. frame 89hz provides 89hz frame frequency. frame 170hz provides 170hz frame frequency. name command code function frame 170hz x 100 -0001-1000-xxxx select 170hz frame frequency frame 89hz x 100 -0001-1101-xxxx select 89hz frame frequency frame 64hz x 100 -0001-1110-xxxx select 64hz frame frequency frame frequency selection command code time base and watchdog timer wdt the time base generator and wdt share the same counter which is divided by 256. the irq clock can be programmed as 1hz, 2hz, ...., 128hz output. timer dis/en/clr, wdt dis/en/clr and irq en/dis are independent from each other. once the wdt time-out occurs, the irq pin will remain at a logic low level until the clr wdt or the irq dis command is issued. if an external clock is selected as the system frequency source, the sys dis command turns out invalid and the power down mode fails to be carried out until the external clock source is removed. ht1650 rev. 1.80 10 november 9, 2010 patented buzzer tone output a simple tone generator is implemented in the ht1650. the tone generator can output a pair of differential driv - ing signals on the bz and bz which are used to generate a single tone. by executing the tone 4k and tone 2k commands there are two tone frequency outputs selectable that can turn on the tone output. the tone 4k and tone 2k commands set the tone frequency to 4khz and 2khz, re - spectively. the tone output can be turned off by invoking the tone off command. the tone outputs, namely, bz and bz , are a pair of differential driving outputs used to drive a piezo buzzer. once the system is disabled or the tone output is inhibited, the bz and the bz outputs will remain at low level. command format the ht1650 can be configured by software setting. there are two mode commands to configure the ht1650 resource and to transfer the lcd display data. the configuration mode of the ht1650 is called com - mand mode, and its command mode id is 100. the command mode consists of a system configuration command, a system frequency selection command, an lcd configuration command, a tone frequency selec - tion command, a bias current selection command, a timer/wdt setting command, and an operating com - mand. the data mode, on the other hand, includes read, write, and read-modify-write opera - tions. the following are the data mode id and the command mode id: operation mode id read data 110 write data 101 read-modify-write data 101 command command 100 if successive commands have been issued, the com - mand mode id can be omitted. while the system is op - erating in the non-successive command or the non-successive address data mode, the cs pin should be set to 1 and the previous operation mode will also be reset. the cs pin returns to 0 , so a new operation mode id should be issued first. ' . # " # , ' . # " ? , 1 " ; 6 : ( # , - # ' ' . # " time base and wdt configurations name command code function tone off x100 -0000-1000-xxxx turn-off the tone output tone 4k x100 -0001-0000-xxxx turn-on the tone output, the tone frequency is 4khz tone 2k x100 -0001-0001-xxxx turn-on the tone output, the tone frequency is 2khz buzzer tone output command code the following are the data mode id and the command id: operation mode id read data 110 write data 101 read-modify-write data 101 command command 100 if successive commands have been issued, the command mode id can be omitted. while the system is operating in the non-successive address data mode, the cs pin should be set to 1 and the previous operation mode will also be reset. the cs pin returns to 0 , so a new operation mode id should be issued first. ht1650 rev. 1.80 11 november 9, 2010 patented bias generator the ht1650 bias voltage belongs to the internal resistor type. it provides two kinds of bias options, namely 1/6 bias and 1/5 bias respectively. it also provides three kinds of bias current options by programming to suitably drive an lcd panel. the three kinds of bias current are large, middle, and small, respectively. usually, large panel lcd can be excellently displayed by large bias current. relatively, it consumes large current when lcd on command is used. small bias current provides low power consumption during on condition when the lcd is normally displayed. the following are the reference value table. when the bias current for lcd is more than large bias current setting. it is recommended to add external cir - cuit to increase driving current. interfacing only six lines are required to interface with the ht1650. the cs line is used to initialize the serial interface circuit and to terminate the communication between the host controller and the ht1650. if the cs pin is set to 1, the data and command issued between the host controller and the ht1650 are first disabled and then initialized. before issuing a mode command or mode switching, a high level pulse is required to initialize the serial inter - face of the ht1650. the db0~db3 are the 4-bit parallel data input/output lines. data to be read or written or commands to be written have to pass through the db0~db3 lines. the rd line is the read clock input. data in the ram are clocked out on the falling edge of the rd signal, and the clocked out data will then appear on the db0~db3 lines. it is recommended that the host controller read correct data during the interval between the rising edge and the next falling edge of the rd signal. the wr line is the write clock input. the data, ad - dress, and command on the db0~db3 lines are all clocked into the ht1650 on the rising edge of the wr signal. there is an optional irq line to be used as an in - terface between the host controller and the ht1650. the irq pin can be selected as a timer output or a wdt overflow flag output by the s/w setting. the host con - troller can perform the time base or the wdt function by connecting with the irq pin of the ht1650. bias vlcd large bias current middle bias current small bias current 1/5 3v 165a7 0 a3 0 a 5v 270a 110a5 0 a 1/6 3v 140a5 5 a2 5 a 5v 225a9 0 a4 0 a internal resistor type bias generator configurations note: the voltage applied to v lcd pin must be equal to or lower than 7v. adjust vr to fit lcd display. timing diagrams read mode (command id code :110) ht1650 rev. 1.80 12 november 9, 2010 patented & : - & 6 % ; $ $ $ 1 & ( 6 & 6 % ; $ $ $ 1 - - - increase driver current configurations note: the external resistors are used to increment the driving current. and the external capacitors are used to keep the bias voltage stable. % " 7 % % % 9 % % % % % % % % % % % % % % 9 7 % % 6 ( 6 6 6 & 6 6 6 6 6 6 6 6 6 6 6 6 6 6 & ( 6 6 & $ : & & & & & & & & & & & & & & & & & & & : & & ; $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ ; $ $ < = < = # < e & : = < e & ; = < e & % = < e & 6 = < e & & = < e & $ = < e 8 = < e 9 = < e 7 = < e ( = < e : = < e ; = < e % = < e 6 = < e & = < = < = # < " = < " = write mode (command id code :101) read-modify-write mode (command id code :101) ht1650 rev. 1.80 13 november 9, 2010 patented % " 7 % % % 9 % % % % % % % % % % % % % % 9 7 % % 6 ( 6 6 6 & 6 6 6 6 6 6 6 6 6 6 6 6 6 6 & ( 6 6 & $ : & & & $ & & & & & & & & & & & & & & $ : & & ; $ $ $ & $ $ $ $ $ $ $ $ $ $ $ $ $ $ & ; $ $ < = < = # < e & : = < e & ; = < e & % = < e & 6 = < e & & = < e & $ = < e 8 = < e 9 = < e 7 = < e ( = < e : = < e ; = < e % = < e 6 = < e & = < = < = # < " 5 = < " 5 = % " 7 % % 9 % % % % % % % % % % % % % 9 7 % % 6 ( 6 6 & 6 6 6 6 6 6 6 6 6 6 6 6 6 & ( 6 6 & $ : & & $ & & & & & & & & & & & & & $ : & & ; $ $ & $ $ $ $ $ $ $ $ $ $ $ $ $ & ; $ $ < = < = # < e ( = < e ( = < e : = < e ; = < e % = < e 6 = < e & = < = < = < = # < " = < " = % 6 & $ < = < e : = < e ; = < e % = < e 6 = < e & = command mode (command id code :100) note: x stands for don t care application circuits host controller with an ht1650 display system *note: the connection of irq and rd pin can be selected depending on the mcu. adjust vr to fit lcd display adjust r (external pull-high resistance) to fit user s time base clock. it is recommended that the internal equivalent capacitance between seg and com of lcd panel should be lower than 10pf. (lcr meter test condition: frequency in 1khz) ht1650 rev. 1.80 14 november 9, 2010 patented % " f f 7 % 6 & & ( 6 f & $ $ $ : & f $ $ # ( # < " = 7 % f 7 % f 7 % f 7 % f 7 % f 7 % f ( 6 f ( 6 f ( 6 f ( 6 f ( 6 f ( 6 f ; $ f : & f : & f : & f : & f : & f : & f : ; % 6 & < " = ; $ f ; $ f ; $ f ; $ f ; $ f ; $ f f # , $ 2 % g ! c ! " ! " # ! " ! 1 ! ' b 1 & < % 6 1 @ a = ' b 1 6 < % 6 1 @ a = " % 6 7 ( 9 @ a + + ! $ 2 ! % & " ' $ 2 " ' ( % g & ( & : 0 & % 6 & & ( g - g - d a b h 7 - instruction set summary name command code d/c function def. read a8 110 -a7a6a5a4a3a2a1a0d3d2d1d0 d read data from the ram write a8 101 -a7a6a5a4a3a2a1a0d3d2d1d0 d write data to the ram read-modify- write a8101 -a7a6a5a4a3a2a1a0d3d2d1d0 d read from and write data to the ram sys dis x 100-0000-0000-xxxx c turn off both system oscillator and lcd bias generator yes sys en x 100-0000-0001-xxxx c turn on system oscillator lcd off x 100-0000-0010-xxxx c turn off lcd display yes lcd on x 100-0000-0011-xxxx c turn on lcd display timer dis x 100-0000-0100-xxxx c disable time base output yes wdt dis x 100-0000-0101-xxxx c disable wdt time-out flag output yes timer en x 100-0000-0110-xxxx c enable time base output wdt en x 100-0000-0111-xxxx c enable wdt time-out flag output tone off x 100-0000-1000-xxxx c turn off tone outputs yes clr timer x 100-0000-1101-xxxx c clear the contents of the time base generator clr wdt x 100-0000-1111-xxxx c clear the contents of the wdt stage tone 4k x 100-0001-0000-xxxx c turn on tone output, tone frequency output: 4khz tone 2k x 100-0001-0001-xxxx c turn on tone output, tone frequency output: 2khz irq dis x 100-0001-0010-xxxx c disable irq output yes irq en x 100-0001-0011-xxxx c enable irq output rc 32k x 100-0001-0100-xxxx c system clock source, on-chip rc oscillator yes ext (x tal) x100-0001-0101-xxxx c system clock source, external 32khz clock source or crystal oscillator 32.768khz large bias x 100-0001-0110-xxxx c large bias current option yes middle bias x 100-0001-0111-xxxx c middle bias current option small bias x 100-0001-1000-xxxx c small bias current option bias 1/6 x 100-0001-1010-xxxx c lcd 1/6 bias option yes bias 1/5 x 100-0001-1001-xxxx c lcd 1/5 bias option frame 170hz x 100-0001-1100-xxxx c selects 170hz frame frequency frame 89hz x 100-0001-1101-xxxx c selects 89hz frame frequency frame 64hz x 100-0001-1110-xxxx c selects 64hz frame frequency yes select 80 16 x100-0001-1111-xxxx c this command will change segment from 64 to 80 and common from 32 to 16 f1 x100-1010-0000-xxxx c time base clock output: 1hz the wdt time-out flag after 4s f2 x100-1010-0001-xxxx c time base clock output: 2hz the wdt time-out flag after 2s f4 x100-1010-0010-xxxx c time base clock output: 4hz the wdt time-out flag after 1s ht1650 rev. 1.80 15 november 9, 2010 patented name command code d/c function def. f8 x100-1010-0011-xxxx c time base clock output: 8hz the wdt time-out flag after 1/2s f16 x100-1010-0100-xxxx c time base clock output: 16hz the wdt time-out flag after 1/4s f32 x100-1010-0101-xxxx c time base clock output: 32hz the wdt time-out flag after 1/8s f64 x100-1010-0110-xxxx c time base clock output: 64hz the wdt time-out flag after 1/16s f128 x100-1010-0111-xxxx c time base clock output: 128hz the wdt time-out flag after 1/32s yes test x100-1111-1111-xxxx c test mode, not for use by the user normal x 100-1111-1110-xxxx c normal mode, 64 32 mode will be set yes note: x stands for don t care a8~a0: ram address d3~d0: ram data d/c: data/command mode def.: power-on reset default all the bold forms, namely, 110 , 101 , and 100 , are mode commands. of these, 100 indicates the command mode id. if successive commands have been issued, the command mode id except for the first command will be omitted. the tone frequency source and the time base or wdt clock frequency source can be derived from an on-chip 32khz rc oscillator, a 32.768khz crystal oscillator, or an external 32khz clock. calculation of the frequency is based on the system frequency sources as stated above. it is recommended that the host control- ler should initialize the ht1650 after power-on reset, otherwise, power on reset may fail, which in turn leads to the malfunctioning of the ht1650. ht1650 rev. 1.80 16 november 9, 2010 patented package information 128-pin qfp (14mm 20mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.669 0.689 b 0.547 0.555 c 0.906 0.925 d 0.783 0.791 e 0.020 f 0.008 g 0.098 0.122 h 0.134 i 0.004 j 0.026 0.037 k 0.004 0.008 07 ht1650 rev. 1.80 17 november 9, 2010 patented & $ % & 6 9 & % 9 % 8 & $ 6 ( : ' ) @ # i ? ( ; symbol dimensions in mm min. nom. max. a 17.00 17.50 b 13.90 14.10 c 23.00 23.50 d 19.90 20.10 e 0.50 f 0.20 g 2.50 3.10 h 3.40 i 0.10 j 0.65 0.95 k 0.10 0.20 07 ht1650 rev. 1.80 18 november 9, 2010 patented ht1650 rev. 1.80 19 november 9, 2010 patented copyright 2010 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com |
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